The present invention relates to data transmission and more specifically to a circuit and method for producing a linear and stable pulse width modulation signal.
In data transmission systems, modulation is the process of encoding analog or digital input data signals onto a carrier signal of a certain frequency f.sub.c. The frequency of the carrier signal is carefully chosen for its compatibility with the transmission medium on which it is sent. The modulated signal is decoded at a receiver to restore the input data signals. An example of an input data signal is a control signal that is modulated by an input data signal and transmitted to an electronic device where the control signal is restored.
One modulation technique is pulse width modulation (PWM) in which a value of an input sample is used to modulate the duration of pulses in an output signal. The carrier signal can be analog, however digital PWM provides greater accuracy and has largely replaced analog PWM in modern electronic applications. In digital PWM, a digital input is counted and used to generate a train of pulses of fixed frequency, with the pulse widths being proportional to the digital input count. A pulse width, or pulse duration, defines a part of what is known as a duty cycle, which is a ratio of a pulse's duration in proportion to the total period.
FIG. 1 is a simplified diagram of a conventional digital pulse width modulation scheme 100 that uses one clock and two counters. A clock source 102 provides a pulse width carrier signal having a fixed frequency f.sub.c. The clock source 102 is provided to two counters 106(a) and (b) simultaneously. A microprocessor or microcontroller 104 loads each counter 106(a) and 106(b) with counts N1 and N, respectively, where N is greater than N1. Counters 106(a) and 106(b) perform a modulo-N count of the N1 and N pulses at each clock pulse f.sub.c. At each N1th count flip-flop 108 is set, and at each Nth count flip-flop 108 is reset, providing an output pulse signal.
FIG. 2 illustrates a digital PWM output pulse signal. With reference also to FIG. 1, at a count of N1, flip-flop 108 is set, and a pulse signal period begins at step 202. At a count of N, flip-flop 108 is reset, and the pulse signal ends at step 204. Again, at a count of N1, the next period begins at step 206, and so on. In FIG. 2, T represents one period of pulse signal 200, and the duty cycle of signal 200 is represented as t.sub.1 /T, which is directly proportional to counts N1 and N. Thus, by changing the value of N1 and N, the duty cycle of signal 200 may be varied.
Most conventional digital PWM circuits do not provide a precise or stable enough duty cycle for more complex electronic device applications. One source of error is having two counters provide the digital input counts on which the duty cycle is based. A second source of error is clock variations carrying over to the output signal. What is needed is digital pulse width modulation that provides a stable and precise duty cycle suitable for providing control to complex electronic devices.